Application Specific Integrated Circuit Engineer

Qualifications:

• Strong experience in SoC Low Power Design / Implementation
• Hands-on expertise with UPF (Unified Power Format)
• Experience with Conformal Low Power (CLP) or similar tools
• Solid understanding of multi-voltage and power domain design
• Proven ability to work across the full ASIC design lifecycle

What You’ll Do

• Drive SoC-level low power implementation across complex ASIC designs
• Define and validate power intent (UPF generation)
• Perform low power verification using Cadence Conformal Low Power (CLP)
• Implement power-aware design techniques, including: Power domains, Isolation strategies, Retention, and level shifting
• Collaborate with cross-functional teams