Best suited to mid-level engineers with expertise in ASIC design flows and performance verification, working in a hybrid Austin-San Jose arrangement.
Derived from job-description analysis by Serendipath's career intelligence engine.
As a Design Verification Engineer at Etched, you'll play a pivotal role in ensuring the robustness and performance of custom IPs in SoC designs, working closely with cross-functional teams to validate and optimize hardware and software interactions, making you a key player in the development of cutting-edge AI inference systems.
Original posting from Etched via Ashby
About Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Key responsibilities
- Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
- Work closely with software and application developers on identifying performance bottlenecks and tuning the software.
- Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
- Improve and maintain the architectural performance models.
- Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
- Develop SystemVerilog or Python-based checkers for verifying the performance features.
- Develop coverage monitors and analyze coverage to ensure all performance features are covered.
- Debug performance issues and conduct performance tuning on silicon.
- Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.
You may be a good fit if you have
- Strong understanding of digital design, RTL, and ASIC design flows.
- Hands-on experience with performance verification, simulation, and modeling.
- Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
- Skilled in writing Python scripts for automation, data analysis, and performance modeling.
- Experience building and maintaining performance models for chip subsystems.
- Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.
- Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
- Some exposure to kernel level performance metrics and profiling tools.
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch + dinner in our office
How we’re different
Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
Source: Etched careers (Ashby)