Junior RTL Engineer for AI Accelerator Co-Design

A leading AI organization in San Francisco is seeking an RTL Engineer to design components for their custom AI accelerator. Candidates should have experience in hardware-software co-design and a strong background in Verilog/SystemVerilog. This hands-on role offers the opportunity to work within a hybrid model, contributing to the next generation of AI hardware solutions. The compensation range is competitive, promising a dynamic and innovative work atmosphere.