Physical Design Engineer

Etched
US
Remote

Who this role is best for

Best suited to mid-level Physical Design engineers with expertise in advanced process nodes and automation, working in AI hardware startups with hybrid office presence.

Best fit for

  • Engineers who thrive in fast-paced AI hardware startups with hybrid office requirements.
    — “Startup experience or comfort working in fast-paced environments
  • Candidates with deep expertise in back-end design and timing closure on 5nm and below.
    — “Experience with back-end design and timing closure on advanced process nodes (5nm and below)
  • Professionals who can supervise 3rd party design work and improve CAD infrastructure.
    — “Supervise the outsourcing of physical design to a 3rd party service

Things to consider

  • Initial heavy travel commitment with two weeks per month in San Jose for ramp-up.
    — “During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters
  • Ongoing monthly travel requirement post-ramp, with one week per month in San Jose.
    — “After that, this shifts to roughly one week per month for ongoing collaboration

How to stand out

  • Demonstrate experience with transformer models and machine learning in your portfolio.
    — “Familiarity with transformer models and machine learning
  • Highlight scripting skills in Python to showcase automation capabilities.
    — “Ability to program with Python or another scripting language
  • Emphasize first-principles thinking in problem-solving approaches.
    — “Deeply creative and able to think from first principles
Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · TeamLevel · Mid

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • Block-level implementation and verification
  • Drive timing closure and PPA optimization
  • Supervise 3rd party design work
  • Improve design flows and iteration speed
Typical background
5-10+ years of previous experience with Physical DesignExperience with back-end design and timing closure on advanced process nodes (5nm and below)

Skills & requirements

Required

Physical DesignCadence (innovus, Genus)Synopsys (icc2, Fusion Compiler)Upf-based Low Power Design MethodologySign-off Tools (primetime, Tempus, Voltus)

Preferred

Transformer ModelsPythonAI Tools For Programming/codingStartup Experience

Stack & domain

Cadence (innovus, Genus)Synopsys (icc2, Fusion Compiler)PrimetimeTempusVoltusUpf-based Low Power Design MethodologyPower VerificationSynthesisScan Insertion/atpgFormal VerificationFloorplanningPlacementCtsRoutingIr DropEm/antenna AnalysisCollaborationCreativityProblem-solvingAsicTransformersMachine Learning

About the role

As a Physical Design Engineer at Etched, you'll be at the forefront of developing cutting-edge AI inference systems, working closely with a team of top-tier engineers to optimize and verify block-level designs, ensuring high performance and efficiency in advanced process nodes.

Original posting from Etched via Ashby

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you

will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities

  • Deeply understand what is involved in physical design
  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,

improve CAD infrastructure

  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
  • Drive dashboards that show the convergence of projects related to PD
  • Optimize tool flows, working with EDA vendors to incorporate the latest features
  • Accountable for block level closure
  • Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

  • 5-10+ years of previous experience with PD
  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
  • Experience with back-end design and timing closure on advanced process nodes (5nm

and below)

  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)

automated RTL-to-GDSII flows

  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,

routing, IR drop, and EM/antenna analysis

  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with transformer models and machine learning
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office

How we’re different:

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

Source: Etched careers (Ashby)

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