Principal DFT Engineer (Silicon Engineering)

SpaceX

Austin, US

On-site

Who this role is best for

Aimed at senior ASIC engineers with 10+ years of DFT experience who thrive in cross-disciplinary teams and extended work hours.

Best fit for

Senior DFT engineers with leadership experience in SOC execution from concept to deployment.
— “Leadership experience driving SOC DFT execution from concept through tapeout and product deployment”
Candidates proficient in Siemens Tessent tools for RTL and gate netlist DFT implementation.
— “leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation”
Engineers with strong problem-solving skills for clock domain crossings and power optimization.
— “Ability to solve complex problems including clock domain crossings and power optimization”

Things to consider

Must be a U.S. citizen or eligible for ITAR compliance.
— “To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national”
Requires willingness to work extended hours and weekends for critical milestones.
— “Ability to work extended hours and weekends as needed to meet critical milestones”

How to stand out

Highlight experience with ATE testers and test teams in your resume.
— “Experience working with ATE testers and test teams”
Emphasize any RTL debugging experience related to DFT connectivity issues.
— “RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT”
Showcase automation skills with Perl, Python, Tcl, or C+ in your application.
— “Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+”

Pace · SteadyCollaboration · HighAutonomy · HighDecision Impact · TeamLevel · Principal

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

Led implementation and optimization of DFT architectures
Owned ATPG tools and methodologies
Evaluated design readiness for scan insertion
Integrated and verified DFT fabrics and IP

Typical background

ASIC designDFT engineeringRTL design

Skills & requirements

Required

DFT ArchitecturesScan InsertionCompression/decompression LogicMemory BISTLogic BISTATPG ToolsPattern GenerationPost-silicon TestingRTL And Gate Level SimulationsProgramming Languages

Preferred

Formal VerificationDRC Rule CheckingUPF

Stack & domain

Dft ArchitecturesScan InsertionCompression/decompression LogicMemory BistLogic BistAtpg ToolsPattern CompressionDiagnosisHierarchical Test FlowsPost-silicon TestingValidationRtlGate Level SimulationsTest ScriptsAutomationProgramming LanguagesAsicsUpfFormal VerificationDrc Rule CheckingAdvanced Silicon ProcessHigh Speed And Low Power ConsumptionVerilog/systemverilogAte TestersTest TeamsLeadershipProblem-solvingComplex Problem-solvingCollaborationCross-disciplinary TeamsDftStarlinkSatelliteBroadband InternetSpaceGround Infrastructure

About the role

Original posting from SpaceX via Greenhouse

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   
RESPONSIBILITIES:
Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Run and debug non-timing and SDF annotated gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+
BASIC QUALIFICATIONS:
Bachelor’s degree in electrical engineering, computer engineering or computer science
10+ years of experience working with ASICs
10+ years of experience in scan insertion and DFT setup, integration and validation
PREFERRED SKILLS AND EXPERIENCE:
Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
Ability to solve complex problems including clock domain crossings and power optimization
Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
Familiar with advanced silicon process and technology nodes for high speed and low power consumption
Strong implementation or integration of design blocks using Verilog/SystemVerilog
Experience working with ATE testers and test teams
ADDITIONAL REQUIREMENTS:
Ability to work extended hours and weekends as needed to meet critical milestones   
ITAR REQUIREMENTS:
To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com. 

Source: SpaceX careers (Greenhouse)