Senior AI ASIC Design Engineer: End-to-End RTL & Subsystems

A leading technology firm in Dubai is seeking a Senior ASIC Design Engineer to lead the design of critical AI ASIC subsystems from start to finish. The successful candidate will have over 7 years of experience, strong Verilog expertise, and a hands-on approach to the entire chip development lifecycle.

Responsibilities include designing and implementing complex subsystems, collaborating with various engineering teams, and ensuring high code quality. This role offers a fast-paced environment contributing to real-world AI workloads.