Job Highlights
- Timing IC Design
- BSc in E.E
- 3 years in Mixed Signal Senior IC Design
Job Description
- Understand design specifications and product architectures.
- Design, simulate and verify analog/digital circuits for low jitter PLL, PFD Link, digital filter, Fraction N divider, Fractional Output Divider (FOD) and high- performance output buffer using deep submicron CMOS process technology.
- Create and verify the high-level architecture by Matlab / VerilogA / Verilog.
- Work with Project Leader. Supervise layout work. Work with Product/Test/Application Teams for product characterization, post silicon verification and Customer support.
- Create and maintain documentation for the related Projects.
Requirements
- Bachelor Degree or above in Electronic Engineering
- M.S.E.E preferred
- 3 – 8 years in analog chips design
- Solid knowledge in CMOS mixed signal circuit design.
- Familiar with IC development and verification tools, e.g., Cadence CAD tools, Hspice, Matlab, Spectre and etc.
- Has experiences of standard output buffer such as LVPECL, LVDS, HCSL, CMOS design.
- Having experiences of Fraction Output Divider (FOD) is a plus.
- Good communication and interpersonal skills, while being motivated to take the initiative to drive for results and closure.
- Good in oral and written Chinese (Cantonese and Mandarin) and English.
- Being a senior engineer or an engineer depending on qualifications and experience
Interested parties, please send application letter and full resume with date of availability, current and expected salary. Please also quote the reference number on the application.
Personal data provided will be treated in strict confidence and used for recruitment purpose only. Only shortlisted candidates will be notified. Applicants not invited for interview within eight weeks from the date of application may consider their applications unsuccessful.