Senior/Lead FPGA Acceleration Engineer (LLM on FPGA)

China Telecom Singapore Innovation Research Institute
Singapore, SG

Why this role

Pace
Fast Paced
Collaboration
High
Autonomy
High
Decision Impact
Company
Role Level
Team Lead

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • successful FPGA-based AI acceleration
  • optimized hardware designs
Typical background
FPGA designAI hardware acceleration

Transferable backgrounds

  • Coming from FPGA engineer
  • Coming from AI hardware engineer

Skills & requirements

Required

FPGA DevelopmentAI On FPGAHLSVivado/vitis

Preferred

Knowledge Of AMD Accelerator CardsPython Domain-specific Language

Stack & domain

VhdlVerilogSystemverilogHlsPythonVivadoVitisPcieMigDmaDigital Signal ProcessingAIFpgaLLM

About the role

Original posting from China Telecom Singapore Innovation Research Institute

About the job

【About the Role】

Join our pioneering team to redefine the future of local inference for AI models and ecosystems. We are building an FPGA-based general computation systems as a superior alternative to GPUs for Large Language Model (LLM) acceleration in Edge and Open Radio Access Network (O-RAN) environments. You will lead the hardware design, optimizing and accelerating high-performance AI inference on FPGA-based platforms.

【Key Responsibilities】

  • FPGA Development:

Architect, optimize, and develop hardware acceleration designs for local inference of LLMs on AMD FPGA platforms. Perform synthesis, place-and-route, timing closure, and power analysis. Debug FPGA-related issues using built-in logic analyzers with JTAG debuggers.

  • IP Development and Integration:

Develop/optimize key IPs such as MIGs/PCIe/DMA cores/parallel computing entities at RTL. Create testbenches and verification environments for a full IP validation.

  • Integration & Validation:

Support System-level integration, work alongside software engineers to transfer algorithms into FPGA hardware designs, using proper acceleration/ HDL languages. Perform end-to-end system-level testing, generate design description and testing documentations.

【Technical Requirements】

  • Hardware:

5+ years of experience in

VHDL/Verilog/SystemVerilog

or

HLS

, especially in acceleration for parallel computation and/or neural networks. Expert in timing closure and resource optimization for large-scale FPGAs.

  • AI background:

Understanding of architectures for Neural Networks such as CNNs/Transformers.

  • Tools:

Mastery of Vivado/Vitis, and Python-based AI frameworks (PyTorch/TensorFlow).

  • Interface & Protocols:

Proficiency in

PCIe

,

10/25/100G Ethernet

,

MIG

and

DMA

cores.

  • Understanding of

digital signal processing (DSP)

fundamentals is a plus.

【Preferred Qualifications】

  • Direct experience with

AMD Accelerator cards

for neural network acceleration applications.

  • Knowledge of

HLS

for parallel computation/neural networks.

  • Knowledge of

Python Domain-Specific Language

for parallel computation/neural networks.

【What We Offer】

  • Opportunity to work on "World-First" AI-RAN integration projects.
  • Collaborative environment with top-tier AI researchers and Telecom experts.
  • Competitive salary and equity packages.

About the Company

China Telecom Singapore Innovation Research Institute stands as the first overseas R&D center of China Telecom, driving innovation in next-generation technologies.

Located in Singapore—a global hub for technology and research—the institute focuses on pioneering advancements in 6G and network AI. By fostering collaboration with industry and academic partners, we aim to promote the development of a comprehensive ecosystem and cutting-edge solutions in digital technology, operating technology, information technology, and communication technology on a global scale.

Source: China Telecom Singapore Innovation Research Institute careers

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