SLT Test Engineer - ASIC

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

Our Taiwan team is seeking a skilled SLT Test Engineer to develop, implement, and maintain the test programs and hardware for our high-throughput AI ASICs on the System-Level Test (SLT) platform. You will be a key member of the Manufacturing Test Engineering team. Your work supporting test at our partner will help ensure test integrity and the quality in the test process, predictability in all steps required of our partner(s), and ultimately performance of our chips before they are integrated into server systems. This role requires hands-on experience in post-silicon validation and a deep understanding of test methodology for complex digital and mixed-signal devices.

You will collaborate closely with the ASIC design, product engineering, test and manufacturing engineering teams to bring up new chips, debug failures, optimize test coverage for volume production, perform test validation prior to introduction of coverage changes, drive test partner in prescriptive maintenance and handling requirements. You will work with tester manufacturer as a primary SME in Taiwan from Etched to ensure all testers are 100% operational.

Key responsibilities

• Assist in the development and debug production test programs (software and hardware) on System-Level Test (SLT) platforms for new ASIC products.

• Design and validate SLT-specific hardware, including load boards, handlers, and thermal control solutions.

• Execute characterization and qualification plans, analyze data, and drive continuous improvement in test coverage, yield, and throughput.

• Collaborate with design and product engineering teams to resolve silicon issues, test platform instabilities, and correlation gaps.

• Institute maintenance and correlation activities with OEM SLT company and test partner.

• Manage test data, generate reports, and ensure all test processes comply with quality and manufacturing requirements.

• Support the transition of new test programs and hardware from NPI (New Product Introduction) to high-volume manufacturing (HVM).

• Proactively identify and implement improvements to test efficiency and cost reduction with Engineering review and acceptance.

You may be a good fit if you have

• Minimal of 5+ years of hands-on experience in System-Level Test (SLT) or ATE (Automated Test Equipment) for complex semiconductor devices, such as ASICs or CPUs/GPUs.

• Proven programming skills in Python, C++, or similar languages for test program development and data analysis.

• Strong understanding of digital and mixed-signal circuits, fault models, and test methodologies (e.g., DFT, BIST).

• Familiarity with server architectures, high-speed interfaces (e.g., PCIe, DDR), and data center hardware.

• Comfortable working closely with hardware in a lab or factory setting for debug and bring-up.

• Excellent communication skills and cross-functional coordination capability.

Strong candidates may also have experience with

• Experience with Chroma SLT testers

• Experience with high-throughput test environments and optimizing test time for cost.

• Familiarity with reliability testing methods (e.g., Burn-in, HAST).

• Background in Product Engineering or Yield Management.

• Experience with advanced statistical data analysis tools.

Benefits

• Competitive compensation packages including generous equity packages

• Comprehensive insurance coverage and other top-of-market benefits

• US Onboarding experience in our Silicon Valley HQ

How we’re different

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.