Sr. / Staff Electrical Engineer (ASIC design)

Responsibilities: Experienced in RTL design and verification Experienced with ATPG Working knowledge of Verilog and System-Verilog. Scripting experience in TCL, perl, Skill, Python. Working knowledge of semiconductor device physics and transistor characteristics. Experienced in mixed-signal ASIC physical design: synthesis, place & route, STA, formal verification, power analysis, manual ECO, automated ECOs, etc. Qualifications: Bachelor’s degree in electrical engineering or equivalent practical experience 15 years of experience in ASIC design, 5+ years of experience in RTL to GDS for mixed-signal ASICs. 5+ years of experience in automotive ASIC projects (IATF-16949). Preferred experience with functional safety (ISO-26262) Preferred experience in low-power design. Preferred experience in Cadence tools, and open-access flows.)

Hardware Engineering