Must be a US Citizen or Green card holder to qualify
We are seeking an experienced engineer to handle verification and behavioral modeling for complex mixed-signal ICs.
Key Responsibilities:
- Develop verification plans and testbenches using SystemVerilog
- Create accurate behavioral models for analog and mixed-signal circuits (ADC, DAC, LDO, charge pumps, etc.)
- Run simulations, perform equivalence checks, and debug results
- Collaborate closely with design teams to resolve issues
- Write automation scripts (Python/Perl) and support tapeout sign-off
Requirements:
- BS in Electrical Engineering + 5+ years relevant experience
- Strong SystemVerilog and mixed-signal verification skills
- Experience with SPICE, HDL simulation, and logic equivalence tools
- Good scripting/programming skills (Python, Perl, or C)
- Solid understanding of analog/mixed-signal architectures
- Excellent debugging and teamwork skills
Analog behavioral modeling experience is a plus.
If you're strong in mixed-signal verification and modeling, we'd love to talk!