Analog/Mixed Signal System Test Engineer Intern

Astera Labs
San Jose, CA
On-site

Who this role is best for

Best suited to candidates with advanced EE degrees and hands-on experience in high-speed mixed-signal circuits working in semiconductor design and validation.

Best fit for

  • Candidates with advanced EE degrees and strong hands-on experience in high-speed analog design
    — “Pursuing a Master’s or PhD degree in EE is preferred”
  • Those with prior experience in advanced CMOS node design and validation
    — “Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a plus”

Things to consider

  • This role is likely to be in-person, given the housing stipend and lab equipment requirements
    — “U.S. interns currently receive a $500-per-week housing/relocation stipend”
  • Commitment to full-time lab work and data analysis is expected due to the technical demands
    — “Strong experience in lab chip bring-up, automation, data collection, data analysis and debugging efforts.”

How to stand out

  • Highlight independent project outcomes and technical depth in analog circuit validation
    — “Strong technical independent contributor with a proven ability to drive results.”
  • Demonstrate expertise in Python, MATLAB, or C through tangible automation or analysis projects
    — “Excellent programming/scripting ability in Python, Matlab, or C.”
  • Showcase experience with high-speed mixed-signal circuits like ADCs, PLLs, and CDRs
    — “Hands-on experience in designing or validating high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must”
  • Emphasize research publications or patents in analog or RF IC design if available
    — “Relevant research publications and/or patents in analog or RF IC design.”
Pace · SteadyCollaboration · MediumAutonomy · MediumDecision Impact · Individual

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • Verify circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs for electrical and optical interconnect to meet performance targets.
Typical background
Pursuing a Master’s or PhD degree in EE

Skills & requirements

Required

High-speed Mixed-signal CircuitsLab Chip Bring-upAutomationData CollectionData AnalysisDebuggingLab Equipment (uxr, DCA, VNA, PNA, Bert)PythonMatlabCAdvanced CMOS NodesTransistor-level DesignFeedback/stability AnalysisNoise/jitter AnalysisOptical TransceiversTIA DesignDrivers For Optical Applications

Preferred

PCB DesignVerilog RTLDSP Design Concepts

Stack & domain

PLLDLLADCRegulatorsAmplifiersTXRXCdrsHigh-speed Mixed-signal CircuitsAdc/dac Data ConvertersRX Front-endTX Driver/serializerLow-jitter PllsTx/rx CalibrationLow-jitter CLK DistributionLab Chip Bring-upAutomationData CollectionData AnalysisDebugging EffortsLab EquipmentUXRDCAVNAPNABERTPythonMatlabCAdvanced CMOS NodesTransistor-level DesignFeedback/stability AnalysisNoise/jitter AnalysisOptical TransceiversTIA DesignDrivers For Optical ApplicationsPCB DesignVerilog RTLDSP Design ConceptsAnalogMixed-signalSystem Test

About the role

Original posting from Astera Labs via Greenhouse

Job Description:

As an Analog/Mixed-Signal System test Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs for electrical and optical interconnect to meet performance targets. The company seeks a highly motivated designer for this role

Basic Qualifications:

· Pursuing a Master’s or PhD degree in EE is preferred

Desired Experience:

· Hands-on experience in designing or validating high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must

· Strong experience in lab chip bring-up, automation, data collection, data analysis and debugging efforts.

· Experience with lab equipment (UXR, DCA, VNA, PNA, BERT, etc)

· Excellent programming/scripting ability in Python, Matlab, or C.

· Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a plus

· Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.

· Knowledge of optical transceivers, TIA design and drivers for optical applications is highly desirable

· Strong technical independent contributor with a proven ability to drive results.

· Excellent teamwork, presentation, and documentation skills.

· Relevant research publications and/or patents in analog or RF IC design.

· Experience with PCB design is a plus

· Familiarity with Verilog RTL or DSP design concepts is a plus

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $38/hour to $46/hour.

U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship.

Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)

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