ASIC Implementation Specialist

IMC

Amsterdam, Netherlands

On-site

Who this role is best for

Geared toward experienced physical design engineers comfortable with RTL-to-GDSII back-end flows and automation, working in a research-driven environment in Amsterdam with a focus on high-performance ASICs and FinFET nodes.

Best fit for

Candidates with 7+ years of ASIC implementation experience and a track record of successful tapeouts
— “BS/MS in Electrical or Computer Engineering, with 7+ years of ASIC implementation experience and multiple successful tapeouts.”
Individuals who can shape and improve implementation flows through automation
— “Shape and improve implementation flows around design needs, building automation and scripts that support efficient execution.”
Engineers with expertise in advanced FinFET nodes and low-power design flows
— “Advanced FinFET nodes experience (16/12/7/5).”

Things to consider

The role involves working on multiple overlapping projects annually, requiring flexibility and multitasking.
— “multiple overlapping projects each year”
Candidates must be prepared to collaborate closely with cross-functional teams including RTL design and packaging.
— “Work closely with RTL design, DFT, packaging and foundry teams”

How to stand out

Emphasize experience with Cadence and Siemens tools in your resume and interview responses.
— “Hands-on experience with Cadence and Siemens implementation and signoff tools.”
Highlight your ability to drive timing closure and STA for high-performance designs.
— “Drive STA and timing closure for high-performance designs”
Showcase your understanding of power integrity and physical verification processes.
— “Ensure designs are ready for signoff through power integrity analysis, physical verification”

Pace · Fast PacedCollaboration · HighAutonomy · HighDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

take ownership of blocks throughout the RTL-to-GDSII flow
design floorplans and power grids
drive STA and timing closure
ensure designs are ready for signoff
shape and improve implementation flows

Typical background

BS/MS in Electrical or Computer Engineering7+ years of ASIC implementation experiencemultiple successful tapeouts

Skills & requirements

Required

ASIC ImplementationRtl-to-gdsii FlowFloorplanningClock-tree SynthesisSTATiming ClosureSignoffPhysical VerificationLogic Equivalence CheckingEcosDFT AwarenessLow-power Design FlowAdvanced Finfet Nodes

Preferred

Custom Macro IntegrationPackage/pcb Co-designChiplet IntegrationMachine-learning-driven Implementation FlowsRTL CodingFunctional VerificationSynthesis

Stack & domain

Cadence Implementation And Signoff ToolsCMOSRc-parasitic ExtractionPhysical Design Formats And ConstraintsLow-power Design FlowDFT AwarenessRTL Coding AbilityFunctional Verification ExperienceASIC ImplementationHardware Design

About the role

Original posting from IMC via Greenhouse

As an ASIC Implementation Specialist in our Global Hardware R&D team, you’ll help expand IMC’s ASIC capabilities, building on our existing technology to accelerate time-to-market.
You’ll work on greenfield projects spanning cutting-edge research and production-scale implementations, with multiple overlapping projects each year. This is an opportunity to help shape the future of ASICs at IMC and contribute to technology that will support our trading systems over the next decade.
Your Core Responsibilities:
Take ownership of blocks throughout the RTL-to-GDSII back-end flow: synthesis, floorplanning, clock-tree synthesis, timing optimization and signoff.
Design floorplans and power grids, making key decisions around macro and pin placement, area budgeting and clock-tree optimization.
Drive STA and timing closure for high-performance designs, developing and validating the SDC constraints needed to achieve design goals.
Ensure designs are ready for signoff through power integrity analysis, physical verification, logic equivalence checking and ECOs.
Shape and improve implementation flows around design needs, building automation and scripts that support efficient execution.
Work closely with RTL design, DFT, packaging and foundry teams, using physical implementation insights to influence and improve RTL.
Share your expertise through design reviews and clear documentation.
Your Skills and Experience:
Required Experience:
BS/MS in Electrical or Computer Engineering, with 7+ years of ASIC implementation experience and multiple successful tapeouts.
Strong experience across physical implementation and signoff, including floorplanning, clock-tree synthesis, STA, timing closure and physical verification.
Hands-on experience with Cadence and Siemens implementation and signoff tools.
Strong understanding of CMOS, RC-parasitic extraction and key physical design formats and constraints.
Experience with low-power design flow.
DFT awareness.
Advanced FinFET nodes experience (16/12/7/5).
Preferred Experience:
Experience with custom macro integration.
Knowledge of package/PCB co-design, chiplet or 2.5D/3D integration.
Exposure to machine-learning-driven implementation flows.
RTL coding ability and functional verification experience.
Synthesis and DFT experience.
About Us
IMC is a research-driven trading firm where quantitative modeling, machine learning, and engineering shape how modern markets are traded. A stabilizing force in markets since 1989, we provide liquidity across trading venues, delivering the best outcome in value and risk management to investors. Using our own technology and capital, we build proprietary systems and algorithms that operate across global markets. Our researchers, traders, and engineers work as a collective, combining rapid experimentation, advanced infrastructure, and real-time feedback to turn insight into execution and execution into advantage.

Source: IMC careers (Greenhouse)