Design Verification Engineer, New Grad

SambaNova
San Jose, CA
On-site

Who this role is best for

Aimed at new grad candidates with a technical background in digital design and verification who are comfortable with SystemVerilog and UVM.

Best fit for

  • New graduates with a focus on digital design and verification in computer architecture
    — “Coursework or project experience in digital design and computer architecture”
  • Individuals who enjoy debugging and working closely with RTL designers
    — “Debug simulation and regression failures with RTL designers”

Things to consider

  • The role requires a strong grasp of constrained-random verification techniques
    — “Familiarity with constrained-random verification, functional coverage, and assertions”
  • Candidates must be prepared to work with chip-level control and initialization features
    — “Write and execute verification plans for chip-level control and initialization features”

How to stand out

  • Highlight experience with SystemVerilog and UVM in your testbench development projects
    — “Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage”
  • Showcase your understanding of functional coverage and how you've closed coverage gaps in past work
    — “Analyze functional and code coverage and close coverage gaps”
  • Demonstrate proficiency with scripting languages like Python or TCL in verification contexts
    — “Scripting experience in Python, Perl, TCL, or shell”
Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • successful chip verification
  • closed coverage gaps
Typical background
chip verificationdigital design

Skills & requirements

Required

SystemverilogUVMChip-level ControlRTL DesignDebuggingCoverage Analysis

Preferred

AI ToolsMachine Learning

Stack & domain

SystemverilogUVMPythonPerlTCLShellConstrained-random VerificationFunctional CoverageAssertionsClock Domain CrossingCommunicationTeamworkAIChip Design

About the role

Original posting from SambaNova

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the Team

The Design Verification team verifies the RDU, SambaNova's chip for AI workloads. We build SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers.

About the Role

As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.

Responsibilities

Write and execute verification plans for chip-level control and initialization features

Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage

Write directed and constrained-random tests to find corner cases

Debug simulation and regression failures with RTL designers

Analyze functional and code coverage and close coverage gaps

Required Qualifications

B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field

Coursework or project experience in digital design and computer architecture

Experience with SystemVerilog or Verilog

Scripting experience in Python, Perl, TCL, or shell

Experience with UVM

Familiarity with constrained-random verification, functional coverage, and assertions

Familiarity with clock domain crossing concepts

Preferred Qualifications

M.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field

Experience using AI tools such as Claude for verification development and debug

Internship experience in design verification

Base Salary Range:

Base Pay Range$120,000—$150,000 USDSubmission Guidelines

Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. 

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

Source: SambaNova careers

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