FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX
Irvine, CA
On-site

Who this role is best for

A natural match if you have experience in FPGA/ASIC design for space or satellite systems and can work in a collaborative, cross-functional setting.

Best fit for

  • Candidates with experience in space or satellite hardware design and cross-functional teamwork
    — “work alongside world-class cross-disciplinary teams”
  • Engineers who have implemented complex SoC blocks and integrated systems
    — “implementing complex SoC blocks and SoC integration tasks”
  • Individuals with a background in optimizing digital designs for power, performance, and area
    — “Optimize designs for power, performance and area”

Things to consider

  • The role demands compliance with U.S. export regulations and may limit international candidates
    — “To conform to U.S. Government export regulations”
  • Candidates must be prepared for extended hours and mission-critical deadlines
    — “Ability to work extended hours or weekends as needed”

How to stand out

  • Highlight experience with AXI/AHB/APB protocols in your resume and interview preparation
    — “Experience and understanding of AXI/AHB/APB protocols”
  • Emphasize your ability to build tools for analyzing on-orbit and lab data
    — “Contribute to continual improvements to our designs by building physical and digital tools”
  • Showcase your proficiency in SystemVerilog or Verilog with concrete project examples
    — “RTL Design using SystemVerilog, Verilog or VHDL”
  • Demonstrate your experience with EDA tools like VCS, Questa, or Vivado
    — “Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES)”
  • Include examples of debugging complex PCBs with FPGAs and microprocessors
    — “Experience debugging complex PCBs containing Microprocessors and FPGAs”
Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • designing cutting-edge FPGAs and ASICs
  • participating in full design lifecycle
Typical background
electrical engineeringcomputer engineering

Skills & requirements

Required

Fpga/asic DesignVerilog/system VerilogEDA ToolsDigital Communication System Design

Preferred

PythonC/c++Bash

About the role

Original posting from SpaceX via Greenhouse

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog

Optimize designs for power, performance and area

Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation

Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab

Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification

Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:

ASIC/FPGA system integration experience

Proficiency in Python, C/C++, and Bash

Experience in designing DSP, digital communication system datapath blocks, and/or modem design

Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)

Experience and understanding of AXI/AHB/APB protocols

Strong foundation in electrical engineering fundamentals

Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers

Ability to work in a dynamic environment with changing needs and requirements

Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis

Demonstrated ability to work in a highly cross-functional role

Enjoys being challenged and learning new skills

Master’s in Electrical/Computer Engineering or related field

ADDITIONAL REQUIREMENTS:

Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION AND BENEFITS:

Pay Range:

Level 1: $125,000.00 - $160,000.00

Level 2: $145,000.00 - $195,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

ITAR REQUIREMENTS:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com. 

Source: SpaceX careers (Greenhouse)

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