HPC SoC Timing Design Engineer/Leader

Hophr

Japan

Who this role is best for

Strong fit for senior timing design engineers who lead complex SoC projects and collaborate globally, with expertise in STA, SDC, and synthesis tools. The role emphasizes automotive domain knowledge, cutting-edge 3nm process node, and cross-functional teamwork across international design centers.

Best fit for

Senior engineers with experience in automotive SoC timing design and global team leadership
— “global semiconductor company developing flagship automotive SoCs”
Candidates who can manage large-scale digital LSI design and drive process improvements
— “managers are deeply involved in the actual design process, driving product development and improving the development flow”
Individuals with a track record of solving complex timing constraint challenges
— “validation of timing constraints using commercially available STA tools and in-house developed tools”

Things to consider

The role requires a business-level proficiency in either English or Japanese, with conversational fluency in the other
— “Either English or Japanese at a business level (the other at a conversational level)”
The position involves significant collaboration with overseas design centers in English
— “design is carried out in collaboration with design centers in Vietnam and India (language: English)”

How to stand out

Highlight experience in STA, SDC, and logic synthesis with specific tool names and project outcomes
— “Timing design using commercially available STA tools”
Emphasize leadership in complex SoC projects and cross-functional collaboration
— “engineers/leaders who can develop products innovatively”
Demonstrate ability to work in a global team and provide examples of international collaboration
— “collaborate with overseas offices”

Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · TeamLevel · Senior

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

over 5 years of experience in digital LSI design
over 3 years of experience in timing design

Typical background

experience in timing designleadership skills

Skills & requirements

Required

Digital LSI DesignStatic Timing AnalysisTiming Constraint AnalysisLogic Synthesis

Preferred

Verilog-hdlManagement Experience

Stack & domain

STASDCSynthesisStatic Timing AnalysisTiming Constraint AnalysisLogic SynthesisVerilog-hdlLeadershipSolution ProposalGlobal CollaborationSemiconductorAutomotiveAIFunctional SafetySecurity

About the role

Original posting from Hophr via Lever

We're hiring an HPC SoC Timing Design Engineer/Leader for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, cache, memory, high-speed interfaces, AI, video, functional safety, and security — powering the intelligence and electrification of next-generation vehicles.
About the role
High-performance SoC products, also used in automobiles, are key components for realizing the electronic and high-performance capabilities of vehicles, exemplified by "CASE" (Connected, Autonomous, Shared, and Electric). With the increasing demand for improved functionality and performance, SoCs are becoming larger and more complex. Competition is intensifying with the entry of semiconductor vendors from non-automotive sectors, making cost competitiveness a challenge.
From a timing design perspective, efficient development of large-scale, complex SoC products with short turnaround times is essential, and we are seeking engineers/leaders who can develop products innovatively. Furthermore, since design is carried out in collaboration with design centers in Vietnam and India (language: English), we are looking for engineers who can thrive globally.
Responsibilities:
Design Engineer or Design Leader for SoC Timing Design (STA, SDC, Synthesis). Timing design (static timing analysis, timing constraint analysis, logic synthesis technology development, product application).
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Static timing analysis: Timing design using commercially available STA tools.
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Timing constraint analysis: Validation of timing constraints using commercially available STA tools and in-house developed tools.
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Logic synthesis: Logic synthesis using commercially available logic synthesis tools.
★In all cases of static timing analysis, timing constraint analysis, and logic synthesis, they collaborate with overseas offices.
Job Satisfaction:
In Physical Design roles, managers are deeply involved in the actual design process, driving product development and improving the development flow. Working closely with the design team, you will play a crucial role in finalizing LSI product designs.
They utilize the cutting-edge 3nm process node for automotive applications, and they pride themselves on offering top-level challenges and rewards in digital backend design. Furthermore, their collaboration with overseas EDA vendors and design centers allows you to participate in their work as part of a global organization.
Desired Candidate Profile:
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Those who have the attitude to face difficulties head-on.
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People with strong leadership skills.
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Someone who can see the big picture.
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Those with strong solution proposal skills.
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Those who are comfortable using English in their work.
Qualifications:
【MUST】
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Over 5 years of experience in digital LSI design (including over 3 years of experience in timing design (static timing analysis, timing constraint analysis)).
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Either English or Japanese at a business level (the other at a conversational level).
【WANT】
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Understanding hardware description languages (e.g., Verilog-HDL)
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Experience using English in a professional setting
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Management experience
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Those interested in management in the future
Additional Information:
*Details regarding the scope of changes to the work location and the scope of duties to be performed will be provided during the selection process.
Location: Kodaira, Japan

Source: Hophr careers (Lever)