Principal Digital Design Engineer

Astera Labs

San Jose, CA

On-site

Who this role is best for

Aimed at senior-level digital design professionals with expertise in high-speed communication protocols and silicon development, who can work independently and contribute to complex front-end design processes in San Jose, California.

Best fit for

Individuals with deep knowledge of high-speed protocols and strong hands-on front-end design skills
— “Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.”
Those who can take ownership of projects and work with minimal supervision in a collaborative environment
— “Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.”

Things to consider

The role requires immediate availability and authorization to work in the US, limiting options for non-US-based candidates.
— “Authorized to work in the US and start immediately.”
The position demands a high level of independence and ownership, which may not suit those who prefer close team oversight.
— “work with minimal guidance and supervision”

How to stand out

Highlight your experience in full-chip or block-level design ownership with specific examples of production-ready silicon.
— “Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production”
Demonstrate your ability to manage multiple tasks and prepare for customer interactions in your resume and interview responses.
— “Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance”
Showcase your familiarity with Synopsys and/or Cadence tools and your ability to work with them in complex designs.
— “Experience with Synopsys and/or Cadence digital design tools/flows”
Emphasize your silicon bring-up and debug expertise, particularly in small-geometry CMOS processes.
— “Silicon bring-up and debug expertise”
Include any relevant firmware development or scripting experience, especially with C or Python.
— “Firmware development with C-language, scripting with Python or other equivalent programming languages.”

Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

developed micro-architecture and implementation of front-end circuit design
supported complex SoC/silicon products

Typical background

Master’s degree in Electrical Engineering

Skills & requirements

Required

Digital DesignRTLSynthesisDFTUVMPcieEthernet

Preferred

Firmware DevelopmentPythonPcie Or Ethernet Switch Products

Stack & domain

Digital DesignMicro-architectureRTLSynthesisIP IntegrationBlock-level VerificationPci-expressUalinkEthernetDesign For Test (dft)UVMSilicon Bring-upDebugCXLPcieFirmware DevelopmentPythonC-languageScriptingPcie Or Ethernet Switch ProductsLeadershipMentorshipCollaborationInnovationTechnical CommunicationDocumentationNetwork ControllersASICNetworkingServerStorageSilicon ProductsHigh-speed ProtocolsDesign For Test

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
+8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.
Required Experience:
Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Synopsys and/or Cadence digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design
Preferred Experience:
Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.
The base salary range is $185,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)