Principal Verification Engineer

Astera Labs

San Jose, CA

On-site

Who this role is best for

Best suited to experienced verification engineers with a focus on server and networking ASICs working in high-performance computing environments.

Best fit for

Experienced verification engineers with a track record in full lifecycle verification of server and networking ASICs.
— “full lifecycle verification—from planning and test development to debugging and coverage closure”
Candidates with deep expertise in SystemVerilog/UVM and strong debugging skills for complex SoCs.
— “Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle”

Things to consider

The role likely expects a high level of independent work and minimal supervision.
— “ability to work independently with minimal supervision”

How to stand out

Highlight experience with emulation platforms and hardware-software co-verification in your resume.
— “Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms”
Emphasize your ability to close functional coverage gaps and debug complex test failures.
— “Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification”
Showcase your background in packet processing and switching architectures for networking applications.
— “Familiarity with verification of switching architectures, including packet processing and forwarding engines”
Demonstrate your leadership in driving verification strategies and methodologies for SoCs.
— “Drive verification strategy and methodology for SoCs in server and networking applications”

Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

Successfully verified complex ASIC designs
Improved verification methodologies and coverage

Typical background

Experience in SoC verificationExpertise in verification tools and methodologies

Skills & requirements

Required

ASIC VerificationSystemverilogUVMTest PlanningDebugging

Preferred

Emulation PlatformsHardware-software Co-verification

Stack & domain

SystemverilogC/c++PythonASIC VerificationUVMEmulation PlatformsHardware-software Co-verificationProblem-solvingCollaborationDebuggingCoverage AnalysisCommunicationSoc Verification

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
Key Responsibilities
Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
Work with RTL designers to troubleshoot and resolve design issues.
Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
Bachelor’s degree in Electrical Engineering (Master’s preferred).
8+ years of experience in SoC verification, particularly for server and networking applications.
Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
Proficiency with industry-standard simulators, version control, and regression systems.
Strong debugging and coverage analysis skills.
Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
Knowledge of Ethernet/PCIe switching and central buffer architectures.
Experience with emulation platforms and hardware-software co-verification
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)