Senior Digital Design Engineer

Astera Labs

San Jose, CA

On-site

Who this role is best for

Best suited to candidates with a strong background in digital design and high-speed communication protocols working in AI infrastructure and semiconductor technologies.

Best fit for

Candidates with prior experience in high-speed protocol design and silicon bring-up for network controllers
— “Proven front end design skill – architecture, RTL, simulations and synthesis”
Individuals with a background in digital design tools like Synopsys or Cadence
— “Experience with Synopsys and/or Cadence digital design tools/flows”
Candidates who have worked on silicon bring-up and debug for complex systems
— “Silicon bring-up and debug experience”

Things to consider

Must be authorized to work in the US and able to start immediately
— “Authorized to work in the US and start immediately”
The role likely demands deep technical expertise in hardware design and verification
— “Familiarity with UVM based design verification”

How to stand out

Highlight experience with PCIe, Ethernet, or UALink protocol implementation in your resume
— “Hands-on, prefer knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.”
Showcase your experience with design for test (DFT) methodologies in your application materials
— “Knowledge of design for test (DFT)”

Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

Develop micro-architecture and implementation of front-end circuit design
Proven front-end design skill

Typical background

Bachelor’s degree in EEMaster’s degree in EE

Skills & requirements

Required

Digital Design EngineerMicro-architectureFront-end Circuit DesignRTLSynthesisIP IntegrationHigh-speed ProtocolsPcieUalinkEthernetSynopsysCadenceDFTUVM Based Design VerificationSilicon Bring-up And Debug

Preferred

PythonPcie Or Ethernet Switch Products

Stack & domain

Pci-expressUalinkEthernetSynopsysCadenceUVMPythonLeadershipCommunicationSemiconductorNetwork

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration for high performance network controllers. The candidate is preferred to have knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks.
Entrepreneurial, open-mind behavior and can-do attitude.
Authorized to work in the US and start immediately.
Required Experience:
Hands-on, prefer knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
Proven front end design skill – architecture, RTL, simulations and synthesis
Experience with Synopsys and/or Cadence digital design tools/flows
Knowledge of design for test (DFT)
Familiarity with UVM based design verification
Silicon bring-up and debug experience
Preferred Experience:
Scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)