Senior Post Silicon Validation Engineer (Bringup)

Graphcore
Austin, TX
On-site

Who this role is best for

A natural match if you have post-silicon validation experience in digital ASIC environments.

Best fit for

  • Candidates with post-silicon validation experience in digital ASIC environments and a track record of leading technical improvements
    — “architect and drive implementation of continuous improvements to test infrastructure and processes”
  • Individuals with expertise in bare metal C/C++ and a history of working on FPGA/Emulator validation platforms
    — “Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon”
  • Candidates comfortable with cross-functional collaboration and reporting to program management regularly
    — “reporting project status/progress to program management on a regular basis”

Things to consider

  • The role requires working with first silicon and debugging complex hardware-software interactions
    — “Deploy silicon validation tests on first silicon and debugging them”

How to stand out

  • Highlight experience with silicon bringup and post-silicon validation in your resume and interview stories
    — “supporting new product introductions and post-silicon validation”
  • Demonstrate your ability to build and optimize automated test frameworks using Python
    — “Develop automated test framework and regression test suites in Python”
  • Showcase your expertise in embedded C/C++ and FPGA/Emulator platforms in your application materials
    — “Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator”
  • Emphasize your experience with debugging complex hardware-software issues across multiple teams
    — “Ability to work across teams and programming languages to find root causes of deep and complex issues”
Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • Developed and debugged silicon validation tests
  • Deployed tests on first silicon
  • Developed automated test frameworks
  • Implemented best practices in test methodologies
  • Provided feedback to architects
Typical background
Experience in bare metal/embedded C/C++Knowledge of digital ASICsExperience in post-silicon validation process

Skills & requirements

Required

C/c++PythonLinuxASIC ValidationEmbedded SystemsTest InfrastructureDebuggingCollaborationCommunicationProblem-solvingAnalytical SkillsDiagnostic Skills

Preferred

PcieEthernetMemory TechnologiesMixed-signal Building BlocksPllsHigh Speed PhysIC Control/communication Protocols

Stack & domain

Bare Metal / Embedded C/c++Digital AsicsPythonLinuxCommunicationProblem-solvingAnalyticalDiagnosticAI ComputingSemiconductorsData Centre Hardware

About the role

Original posting from Graphcore via Greenhouse

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 

Deploy silicon validation tests on first silicon and debugging them 

Develop automated test framework and regression test suites in Python to optimize validation efficiency 

Collaborate closely with engineers from many other disciplines on a variety of topics 

Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 

Analyse test results, identify and debug failures/defects 

Contribute to shared test and validation infrastructure 

Provide feedback to architects 

Essential skills: 

Strong experience in Bare metal / embedded C/C++ 

Good knowledge of digital ASICs

Be highly motivated, a self starter, and a team player  

Ability to work across teams and programming languages to find root causes of deep and complex issues 

Experience of the post-silicon validation process applied in digital ASIC environments 

Python, Linux 

Excellent communication skills and the ability to collaborate with others to solve problems

Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

Driver level experience with one or more of the following is highly desirable: 

PCIe 

Ethernet 

Memory technologies (LPDDR, DDR, HBM, …) 

Other peripherals such as I2C, I3C, SPI, … 

Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable

Experience of Arm CPUs, System IP and debug tools

Experience of AMBA protocols

Understanding of ML applications and their workloads

Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Source: Graphcore careers (Greenhouse)

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