Senior Silicon Engineer

Clera
San Francisco, CA
On-site

Who this role is best for

Strong fit for experienced digital design engineers who lead FPGA and ASIC development and shape technical direction.

Best fit for

  • Candidates with 8+ years of experience in RTL design and FPGA/ASIC development for AI accelerators
    — “At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.”
  • Individuals who have shaped technical direction in small hardware teams and worked across multiple disciplines
    — “As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.”
  • Engineers with a background in compute datapaths and memory systems under strict performance constraints
    — “Experience designing compute datapaths and memory systems with bandwidth and latency constraints.”

Things to consider

  • On-site commitment in San Francisco is mandatory, with no remote or hybrid options available
    — “Full-time, on-site role in San Francisco, United States. This position is not remote or hybrid.”
  • The role demands full lifecycle ownership of silicon design, including tapeout and bring-up
    — “Drive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.”

How to stand out

  • Highlight your experience with SystemVerilog/Verilog in production silicon or FPGA designs
    — “Experience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs”
  • Emphasize your hands-on contributions during critical design milestones
    — “contributing hands-on during critical periods”
  • Showcase your ability to automate hardware flows using Python, Tcl, or similar tools
    — “Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools”
  • Demonstrate your track record of making architecture decisions for compute and memory systems
    — “Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.”
  • Position yourself as an expert in timing closure and CDC verification
    — “Hands-on experience with ... timing closure, and CDC verification.”
Pace · Fast PacedCollaboration · MediumAutonomy · HighDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • lead FPGA prototype development
  • design and review synthesizable RTL
  • build and improve lint, simulation, synthesis, timing, and verification flows
Typical background
silicon engineeringdigital design

Skills & requirements

Required

RTL DesignASIC DesignFPGA DevelopmentDigital DesignVerification FlowsPythonTclMakeNix

Preferred

AI AcceleratorsLow-level AI Kernels

Stack & domain

SystemverilogVerilogPythonTclMakeNixAI AcceleratorsLow-level AI KernelsSilicon EngineeringRTLASIC

About the role

Original posting from Clera via Ashby

ABOUT THE ROLE

Lead silicon design for an AI accelerator, taking designs from FPGA prototypes through ASIC tapeout and bring-up. As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.

WHAT YOU'LL DO

  • Lead FPGA prototype development and optimization, from design specifications through deployment on working hardware.
  • Design and review synthesizable RTL for an ASIC, with a focus on clean microarchitecture.
  • Build and improve lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
  • Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.
  • Drive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.
  • Mentor teammates and help grow the silicon engineering team.

WHAT WE'RE LOOKING FOR

  • At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.
  • Experience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs, and taking FPGA designs from RTL through synthesis, place-and-route, and deployment to working hardware.
  • Strong understanding of digital design, including pipelining, clocks, resets, latency, throughput, and microarchitecture.
  • Experience designing compute datapaths and memory systems with bandwidth and latency constraints.
  • Hands-on experience with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.
  • Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools, plus background in AI accelerators or low-level AI kernels.
  • Tapeout experience, high-speed interfaces, formal verification, UVM, cocotb, firmware, or systems-level hardware drivers are valuable.

COMPENSATION & BENEFITS

Base salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.

LOCATION

Full-time, on-site role in San Francisco, United States. This position is not remote or hybrid.

Source: Clera careers (Ashby)

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