Senior Wireless Engineer

Neros Technologies

Torrance, CA

Who this role is best for

Strong fit for experienced engineers who implement DSP and communications algorithms in FPGA and SoC environments and work in defense technology.

Best fit for

Candidates with 7+ years of FPGA and embedded C implementation experience in defense or aerospace domains
— “7+ years implementing DSP or communications algorithms in RTL (Verilog/VHDL) and/or embedded C for FPGA or SoC targets”
Individuals who have successfully transitioned MATLAB/Simulink models into production hardware
— “Implement modem and physical-layer blocks from MATLAB/Simulink models into RTL (Verilog/VHDL) and embedded C”
Those with a background in fixed-point conversion and verification against golden reference models
— “Own fixed-point conversion from floating-point models, analyzing quantization, precision, and dynamic-range trade-offs”
Professionals with a deep understanding of hardware-software co-design and partitioning signal chains
— “Partition the signal chain between FPGA fabric and embedded processor, co-designing the hardware/software boundary”

Things to consider

The role demands a high level of precision and ownership in translating models to silicon
— “getting real waveforms onto our drones and working over the air”
Candidates must be prepared for a collaborative, cross-functional approach involving RF and firmware teams
— “Debug the physical layer on captured and live signals alongside the communication systems, RF, and firmware teams”

How to stand out

Showcase your ability to work with FPGA design tools like Vivado/Vitis or Quartus
— “Proficiency with the FPGA design flow: simulation, synthesis, timing closure, and resource optimization (Vivado/Vitis or Quartus)”
Emphasize projects where you implemented complete modems that shipped in hardware
— “Wireless Modems: Hands-on implementation of an end-to-end modem (OFDM, spread spectrum, or single-carrier) that shipped in hardware”

Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

Implemented modem and physical-layer blocks
Owned fixed-point conversion
Optimized FPGA timing and resources
Debugged physical layer on captured and live signals

Typical background

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering

Skills & requirements

Required

DSPDigital CommunicationsFPGASocFixed-point ConversionRTL (verilog/vhdl)Embedded CMatlab/simulinkFPGA Design FlowTestbenchesVerificationTiming ClosureResource OptimizationAXI InterfacesHardware/software Co-design

Preferred

Model-based DesignWireless ModemsSoc IntegrationRf/sdr FamiliarityAdvanced FEC

Stack & domain

MatlabSimulinkCRTLVerilogVHDLFPGASocFixed-point ConversionBit-true ImplementationTestbenchesFPGA Design FlowTiming ClosureResource OptimizationAXI InterfacesHardware/software Co-designRf/sdrLDPCTurboViterbiReed-solomonProblem-solvingCollaborationCommunicationWireless EngineeringModem And Waveform DesignsFPGA And Soc TargetsDigital CommunicationsDSP

About the role

Original posting from Neros Technologies via Greenhouse

Who we are
Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.
As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.
What you will be doing
As a Senior Wireless Engineer, you will turn our modem and waveform designs into real, deployable hardware. Working directly under our Senior Wireless Systems Engineer II, you will take MATLAB/Simulink models of the physical layer and implement them as bit-true, fixed-point designs in C and RTL for our FPGAs and SoCs. You will own fixed-point conversion, verification against the golden reference, and FPGA timing and resource optimization — getting real waveforms onto our drones and working over the air.
Responsibilities
Implement modem and physical-layer blocks — modulation/demodulation, synchronization, equalization, and channel coding/FEC — from MATLAB/Simulink models into RTL (Verilog/VHDL) and embedded C
Own fixed-point conversion from floating-point models, analyzing quantization, precision, and dynamic-range trade-offs
Build bit- and cycle-accurate testbenches that verify RTL and C implementations against the MATLAB/Simulink golden reference
Close timing and optimize LUT, DSP, and BRAM utilization on Xilinx/AMD (or Intel) FPGAs and SoCs
Partition the signal chain between FPGA fabric and embedded processor, co-designing the hardware/software boundary
Debug the physical layer on captured and live signals alongside the communication systems, RF, and firmware teams, working directly with the Principal Communications Systems Engineer to take waveforms from model to silicon
You should have the following
Bachelor of Science in Electrical Engineering, Computer Engineering, or a related field required; Master's degree highly preferred
7+ years implementing DSP or communications algorithms in RTL (Verilog/VHDL) and/or embedded C for FPGA or SoC targets
Strong DSP and digital communications fundamentals: modulation, synchronization, equalization, filtering, and FEC/channel coding
Demonstrated experience with fixed-point conversion and bit-true implementation from MATLAB/Simulink models
Proficiency with the FPGA design flow: simulation, synthesis, timing closure, and resource optimization (Vivado/Vitis or Quartus)
Experience building testbenches and verifying implementations against a golden reference model
Nice to have
Model-Based Design: Generating or hand-optimizing HDL and C from Simulink using MATLAB HDL Coder and Embedded Coder
Wireless Modems: Hands-on implementation of an end-to-end modem (OFDM, spread spectrum, or single-carrier) that shipped in hardware
SoC Integration: Zynq, RFSoC, or similar SoCs, including AXI interfaces and hardware/software co-design
RF/SDR Familiarity: Understanding of the RF front-end, data converters (ADC/DAC), and software-defined radio pipelines
Advanced FEC: Hardware implementation of LDPC, Turbo, Viterbi, or Reed-Solomon decoders
US Salary Range
$187,000 – $261,500 USD
The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.
We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Source: Neros Technologies careers (Greenhouse)