Sr. Staff PCB Design Engineer

D Matrix
Santa Clara
Hybrid

Who this role is best for

Strong fit for high-speed PCB design experts who lead layout infrastructure and automation for AI silicon platforms. Must have deep technical experience in high-layer-count PCBAs and work collaboratively with cross-functional teams in Santa Clara.

Best fit for

  • Candidates with 10+ years of experience in high-speed, high-density PCB layout for AI accelerators or servers
    — “10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
  • Individuals who have led design methodology and automation tooling for complex PCB projects
    — “Serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes
  • Professionals with proven skills in managing high-speed routing constraints and SerDes interfaces
    — “Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines

Things to consider

  • This role is based in Santa Clara, requiring on-site presence for collaboration with ASIC and manufacturing teams
    — “Partner with power, ASIC, and manufacturing teams
  • The position demands working with advanced materials and high-layer-count PCBAs, which may require specialized knowledge
    — “Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups

How to stand out

  • Highlight your experience in managing high-speed interfaces like PCIe Gen5/6 and 112G SerDes in your resume
    — “Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
  • Emphasize your background in constraint management and advanced routing techniques in Allegro
    — “Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • leading full-cycle layout for high-complexity AI accelerator cards
  • architecting and managing the Constraint Manager hierarchy
  • developing automation scripts
  • executing layout for ultra-high-speed interfaces
  • partnering with power and ASIC teams
Typical background
10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI acceleratorsproficiency in Cadence Allegro Constraint Managerproven ability to write and deploy SKILL scripts

Skills & requirements

Required

PCB DesignHigh-speed RoutingConstraint ManagementAutomation ScriptsPower DeliveryPCB Stack-up DefinitionFabrication And CM InterfaceLayout Infrastructure

Preferred

Library Management SystemStandardized Footprint/padstack Creation ProcessesPlm/pdm IntegrationPCB Warpage Mitigation Strategies

Stack & domain

PCB LayoutCadence Allegro Constraint ManagerT-junctionsDifferential Pair Phase-tuningZ-axis Delay MatchingSkill ScriptsPythonTCLDRC ChecksReportingPcie Gen5/6CXLCustom Die-to-die (d2d) InterconnectsPDN StrategyMulti-phase VRM LayoutsDecoupling Capacitor PlacementPCB Stack-up DefinitionAdvanced Low-loss MaterialsHybrid Build-upsFabricatorsCmsDFMDFTDFALibrary Management SystemStandardized Footprint/padstack Creation ProcessesPlm/pdm IntegrationLayout ReleasesECO WorkflowsPCB Warpage Mitigation StrategiesCollaborationAutonomyExecutionProblem-solvingCommunicationTeamworkAI SiliconCorsair PlatformsSignal DensityPower DeliveryHigh-complexityHigh-layer-count Pcbas112g/224g Serdes SignalsAsicsManufacturing TeamsLayout Infrastructure

About the role

Original posting from D Matrix via Ashby

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Role Overview

As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.

What You Will Do

  • Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
  • Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
  • Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
  • Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
  • Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs
  • Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups
  • Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production

What You Will Bring

  • BS in Electrical/Electronic Engineering or equivalent practical experience
  • 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
  • Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
  • Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
  • Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
  • Proven track record routing 112G SerDes and complex DDR5/HBM interfaces

Preferred Qualifications

  • Experience establishing a Library Management System and standardized footprint/padstack creation processes
  • Familiarity with PLM/PDM integration for managing layout releases and ECO workflows
  • Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Source: D Matrix careers (Ashby)

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