Tech Lead Analog Mixed-Signal IC Layout Engineer

Astera Labs

Singapore

On-site

Who this role is best for

Best suited to candidates with a strong VLSI and hardware engineering background working in high-performance compute and networking standards.

Best fit for

Candidates with a strong VLSI and hardware engineering background and experience in advanced CMOS process nodes
— “working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes”
Individuals with hands-on experience in RTL design and verification methodologies like UVM
— “Familiarity with verification methodologies like UVM, functional coverage, assertions”
Candidates who are curious and have a demonstrated ability to learn new technologies and tools
— “Above all, curiosity and ability to learn is a must”

Things to consider

This role requires a strong background in both digital and analog/mixed-signal domains
— “Hardware engineering background with an emphasis in VLSI or Computer Architecture”

How to stand out

Highlight experience with high-speed interfaces such as PCIe, DDR, and Serdes in your resume and interviews
— “Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have”
Demonstrate your ability to work on real-world system design and verification projects
— “experience in design, verification, and validation of real-world systems”
Showcase your hands-on experience with Synopsys EDA tools in your application materials
— “Familiarity with Synopsys EDA tools”

Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

design and/or verification of blocks using leading edge methodology and tools
exposure to high-speed interfaces like PCIe, DDR, HBM, Serdes

Typical background

hardware engineering background with an emphasis in VLSI or Computer Architecture

Skills & requirements

Required

RTL Design LanguagesVerification MethodologiesScripting LanguagesHigh-speed Interfaces

Preferred

Real-world Design And/or Verification In Verilog/system Verilog

Stack & domain

Analog Mixed-signal IC LayoutVLSI DesignComputer ArchitectureRTL Design LanguagesVerification MethodologiesScripting LanguagesHigh-speed InterfacesSynopsys EDA ToolsLeadershipCommunicationTeamworkProblem-solvingStrategic ThinkingSemiconductorAI InfrastructureConnectivity Solutions

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
We are looking for a Analog / Mixed-Signal Layout Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.
Basic qualifications:
Pursuing BS or MS in EE/CS or related fields.
Hardware engineering background with an emphasis in VLSI or Computer Architecture.
Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
Required experience:
Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
Familiarity with verification methodologies like UVM, functional coverage, assertions.
Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.
Preferred experience:
Real-world design and/or verification in Verilog/System Verilog.
Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
Familiarity with Synopsys EDA tools.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)