Tech Lead, Digital Design Engineer

Astera Labs

San Jose, CA

On-site

Who this role is best for

Best suited to candidates with hands-on experience in high-performance switch ASIC design working in AI infrastructure and networking domains.

Best fit for

Candidates with experience in translating microarchitecture to RTL for high-speed connectivity protocols
— “Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.”
Individuals who have led block-level execution from synthesis to GDS delivery
— “Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.”
Candidates with strong track records in front-end digital design for networking and server connectivity
— “Develop front-end design solutions for high-performance networking and server connectivity applications.”

Things to consider

The role requires a strong understanding of multiple high-speed protocols and their integration
— “Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.”
Candidates must be authorized to work in the United States for this opportunity
— “Authorized to work in the United States.”

How to stand out

Highlight your experience with Synopsys and/or Cadence design flows in your resume and interview responses
— “Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.”
Emphasize your ability to resolve complex design tradeoffs across performance, power, and area
— “Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.”
Showcase your leadership in cross-functional projects, particularly with verification and physical design teams
— “Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.”
Demonstrate your ability to manage multiple workstreams and communicate risks effectively to stakeholders
— “Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.”

Pace · SteadyCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

block-level execution through GDS
ability to resolve implementation issues

Typical background

5-8 years of experience in SoC or silicon products

Skills & requirements

Required

RTL DesignHigh-speed ProtocolsDigital DesignSynthesisVerification

Preferred

Uvm-based VerificationPcie Or Ethernet Switch Products Experience

Stack & domain

RTL DesignHigh-speed ProtocolsUvm-based Design VerificationSynopsys And/or Cadence Design ToolsTechnical LeadershipMultiple WorkstreamsCommunicationCustomer-focusedASIC DesignNetworkingServer Connectivity

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.
Key Responsibilities
Digital Architecture and RTL Design
Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
Develop front-end design solutions for high-performance networking and server connectivity applications.
Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
Design Implementation and Signoff
Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
Verification, Bring-Up, and Technical Leadership
Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.
Basic Qualifications
Bachelor’s degree in Electrical Engineering or a related field.
5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.
Authorized to work in the United States.
Preferred Qualifications
Master’s degree in Electrical Engineering or a related field.
Experience developing or supporting PCIe or Ethernet switch products.
Familiarity with UVM-based design verification and coverage-driven debug.
Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.
Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)