Tech Lead, Digital Design Engineer

Astera Labs
San Jose, CA
On-site

Who this role is best for

Best suited to candidates with a strong technical background in digital design and experience in high-performance networking and silicon development working in the AI infrastructure domain.

Best fit for

  • Candidates with a background in high-speed protocol design and block-level ownership of silicon projects
    — “Block level ownership from architecture to GDS.”
  • Individuals with hands-on experience in front-end design and RTL development for network controllers
    — “Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.”
  • Candidates who have worked with Synopsys or Cadence digital design tools and flows
    — “Experience with Synopsys and/or Cadence digital design tools/flows”

Things to consider

  • Must be authorized to work in the US and able to start immediately
    — “Authorized to work in the US and start immediately.”
  • Role likely requires deep technical expertise in multiple high-speed protocols
    — “Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.”

How to stand out

  • Highlight experience with silicon bring-up and debugging in your resume and interview responses
    — “Silicon bring-up and debug experience”
  • Demonstrate your ability to work independently and manage multiple tasks effectively
    — “Professional attitude with the ability to prioritize a dynamic list of multiple tasks”
  • Showcase your track record in developing or supporting complex SoC/silicon products for networking applications
    — “+3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.”
Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · Team

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • micro-architecture and implementation of front-end circuit design
  • block-level ownership from architecture to GDS
Typical background
digital designhigh-speed protocols

Skills & requirements

Required

Digital DesignHigh-speed ProtocolsRTL DesignSynthesisDFT

Preferred

Python ScriptingPcie Or Ethernet Switch Products

Stack & domain

Micro-architectureFront-end Circuit DesignRTLSynthesisIP IntegrationBlock-level VerificationPci-expressUalinkEthernetSynopsysCadenceDFTUVMSilicon Bring-upDebugPythonEntrepreneurialOpen-mindCan-do AttitudeFast ThinkingCustomer FocusDigital DesignNetworkingASICServerStorage

About the role

Original posting from Astera Labs via Greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. 

Job Description 

We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. 

Basic Qualifications: 

Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. 

+3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage. 

Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 

Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! 

Authorized to work in the US and start immediately. 

Required Experience: 

Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc. 

Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc. 

Block level ownership from architecture to GDS. 

Experience with Synopsys and/or Cadence digital design tools/flows 

Knowledge of design for test (DFT) 

Familiarity with UVM based design verification 

Silicon bring-up and debug experience 

Small-geometry CMOS (≤28nm) design 

Preferred Experience: 

Scripting with Python or other equivalent programming languages. 

Development/support for PCIe or Ethernet Switch products. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Source: Astera Labs careers (Greenhouse)

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