Senior ASIC Physical Design Engineer

K2 Space
United States
Remote

Who this role is best for

Best suited to experienced ASIC physical design engineers working in the space and satellite industry, with a focus on remote collaboration and advanced SoC integration.

Best fit for

  • Experienced ASIC physical design engineers with a track record in complex SoC development for space applications
    — “help implement advanced SoCs that power next-generation satellite and space systems”
  • Candidates who have worked with industry-standard physical design tools and can manage full flow execution
    — “Execute the complete physical design flow for complex SoC blocks and top-level integration”
  • Individuals comfortable with cross-functional, geographically distributed team collaboration
    — “work with external physical design service providers and internal leads to review deliverables”

Things to consider

  • Must be a U.S. person or eligible for an export control license due to ITAR restrictions
    — “must therefore either be a 'U.S. person' as defined by 22 C.F.R. § 120.15 or otherwise eligible”
  • The role involves long-term contributions to spaceflight-ready products, requiring a commitment to ongoing development
    — “Support your product through production and spaceflight”

How to stand out

  • Highlight experience with hierarchical or flat SoC design methodologies in your resume and interviews
    — “Experience with hierarchical or flat SoC design methodologies”
  • Emphasize your ability to develop and maintain automation scripts for design efficiency
    — “Develop and maintain scripts and automation to improve flow efficiency and consistency”
  • Showcase your track record in timing closure and optimization across multiple design corners
    — “Perform timing closure and optimization across multiple corners and modes”
  • Demonstrate familiarity with FinFET technologies and physical verification flows
    — “Strong understanding of timing analysis, power optimization, and physical verification flows”
  • Mention any prior work with radiation-hardened or space-qualified ASICs if applicable
    — “Exposure to radiation-hardened or space-qualified ASICs”
Pace · Fast PacedCollaboration · HighAutonomy · MediumDecision Impact · Company

Derived from job-description analysis by Serendipath's career intelligence engine.

What success looks like

  • Implement advanced SoCs for satellite systems
  • Achieve timing closure and PPA optimization
  • Support design integration with external partners
Typical background
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field5–10 years of experience in ASIC physical design

Skills & requirements

Required

ASIC Physical DesignSoc DesignSynthesisPlace & RouteTiming ClosurePPA OptimizationChip-level IntegrationSpacecraft Design

Preferred

Satellite Communications DesignMixed-signal Soc Design

Stack & domain

ASIC Physical DesignSynopsys Icc2/fusion CompilerCadence InnovusTiming ClosurePPA OptimizationChip-level IntegrationSatelliteSpace SystemsMixed-signal Socs

About the role

Original posting from K2 Space via Greenhouse

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  

Responsibilities 

Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 

Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 

Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 

Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 

Develop and maintain scripts and automation to improve flow efficiency and consistency. 

Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 

Assist in chip-level integration, ECOs, and tapeout preparation. 

Contribute to methodology development, tool evaluation, and flow documentation. 

Support your product through production and spaceflight.  

Required Qualifications  

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 

5–10 years of experience in ASIC physical design for complex SoCs. 

Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 

Strong understanding of timing analysis, power optimization, and physical verification flows. 

Experience with hierarchical or flat SoC design methodologies. 

Familiarity with FinFET technologies. 

Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 

Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications  

Exposure to radiation-hardened or space-qualified ASICs. 

Experience with chip-package co-design or advanced packaging (2.5D/3D). 

Familiarity with physical design service vendor management or offshore collaboration. 

Experience with sign-off through TSMC. 

Experience with Gate-All-Around technologies.  

Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

Base salary range for this role is $170,000 – $250,000 + equity in the company

Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level

Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Source: K2 Space careers (Greenhouse)

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